1. Field of the Invention
The present invention relates to a semiconductor processing method and structure thereof. More particularly, the present invention relates to a method of fabricating a metal silicide layer such that different metal silicide materials are formed on different crystalline regions of a substrate.
2. Description of the Related Art
In ultra-high level integration, the size of each semiconductor device is reduced so that the level of integration can continue to increase. After miniaturizing the electronic devices, the semiconductor integrated circuit can have the highest level of integration. However, as the dimension of an electronic device is reduced, a number of challenging problems is encountered in the process of fabricating the integrated circuits. In particular, as devices continue to shrink in size, a reduction in the resistance of electrical connection structures has become increasingly important because any increase in the resistance will directly lead to a slow-down in the operating speed through an increase in RC delay.
To reduce the resistance of connection structures, a self-aligned silicide process is frequently carried out to form a metal silicide layer thereon. Due to the high melting point, stability and low resistance of a metal silicide layer, the use of metal silicide layers in the fabrication of integrated circuits has become increasingly common. In the deep sub-micron regime of integrated circuit fabrication, a polycide gate structure instead of a conventional polysilicon gate structure is often used to improve device operating characteristics, lower resistance and minimize RC delay because line width, contact area and junction depth are all reduced. Furthermore, forming a metal silicide layer over a junction is an effective means of lowering contact resistance at the junction.
In general, a metal silicide film is formed by performing a thermal treatment to a metallic film. The metallic film can be deposited by performing an evaporation process or a sputtering process. Thereafter, the metallic film is annealed by heating inside a furnace or performing a rapid thermal treatment in an atmosphere containing pure inert gases (nitrogen or argon) so that the metal reacts with silicon at their interface to form a metal silicide layer. The most commonly used metal silicide materials include titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, molybdenum silicide and platinum silicide.
Because titanium silicide has a low resistance and is amenable to fine processing control, it is one of the most commonly deployed metal silicide materials. Yet, as the line width of the integrated circuits continues to shrink, the line width of gate lines is reduced correspondingly. With a narrowing of the gate line, the so-called narrow line width effect is increasingly dominant in a titanium silicide layer. When the gate width is lowered to 1 μm or smaller, the sheet resistance of a titanium silicide layer formed on the gate will increase with a decrease in dimension. In other words, the advantage of forming a titanium silicide layer over the gate to lower the sheet resistance is gone. Under these circumstances, titanium silicide layers are replaced using cobalt silicide layers. However, the same problem is encountered when the line width is again reduced. Among the types of metal silicide materials, nickel silicide appears to be the most promising one for replacing cobalt silicide because nickel silicide does not have the aforementioned problem.
Nevertheless, spiking often occurs in the heavily doped P-type region while piping often occurs in the heavily doped N-type region after a nickel silicide layer is formed on an active area.